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XILINX/赛灵思 XC6VLX240T-2FFG1156I 现场可编程门阵列 封装FCBGA-1156 现货

时间:2023-10-05 18:39发布企业:深圳和润天下电子科技有限公司
联系人:蔡经理,张小姐电话:13378422395Q Q:

制造商: Xilinx 
产品种类: FPGA - 现场可编程门阵列 
RoHS:  详细信息 
系列: XC6VLX240T 
逻辑元件数量: 241152 LE 
自适应逻辑模块 - ALM: 37680 ALM 
嵌入式内存: 14.63 Mbit 
输入/输出端数量: 600 I/O 
电源电压-最小: 1 V 
电源电压-最大: 1 V 
最小工作温度: - 40 C 
最大工作温度: + 100 C 
数据速率: 6.6 Gb/s 
收发器数量: 24 Transceiver 
安装风格: SMD/SMT 
封装 / 箱体: FCBGA-1156 
商标: Xilinx 
分布式RAM: 3650 kbit 
内嵌式块RAM - EBR: 14976 kbit 
最大工作频率: 1.6 GHz 
湿度敏感性: Yes 
逻辑数组块数量——LAB: 18840 LAB 
工作电源电压: 1 V 
产品类型: FPGA - Field Programmable Gate Array 

子类别: Programmable Logic ICs 
商标名: Virtex

• Three sub-families: • Virtex-6 LXT FPGAs: High-performance logic with advanced serial connectivity • Virtex-6 SXT FPGAs: Highest signal processing capability with advanced serial connectivity • Virtex-6 HXT FPGAs: Highest bandwidth serial connectivity • Compatibility across sub-families • LXT and SXT devices are footprint compatible in the same package • Advanced, high-performance FPGA Logic • Real 6-input look-up table (LUT) technology • Dual LUT5 (5-input LUT) option • LUT/dual flip-flop pair for applications requiring rich register mix • Improved routing efficiency • 64-bit (or two 32-bit) distributed LUT RAM option per 6-input LUT • SRL32/dual SRL16 with registered outputs option • Powerful mixed-mode clock managers (MMCM) • MMCM blocks provide zero-delay buffering, frequency synthesis, clock-phase shifting, inputjitter filtering, and phase-matched clock division • 36-Kb block RAM/FIFOs • Dual-port RAM blocks • Programmable - Dual-port widths up to 36 bits - Simple dual-port widths up to 72 bits • Enhanced programmable FIFO logic • Built-in optional error-correction circuitry • Optionally use each block as two independent 18 Kb blocks • High-performance parallel SelectIO™ technology • 1.2 to 2.5V I/O operation • Source-synchronous interfacing using ChipSync™ technology • Digitally controlled impedance (DCI) active termination • Flexible fine-grained I/O banking • High-speed memory interface support with integrated write-leveling capability